Microminiature field emission devices are well known in the microelectronics art. These microminiature field emission devices are finding widespread use as electron sources in microelectronic devices. For example, these devices may be used as electron guns in flat panel displays for use in aviation, automobiles, workstations, laptops, head wearable displays, heads up displays, outdoor signage, or practically any application for a screen which conveys information through light emission. Field emission devices may also be used in non-display applications such as power supplies, printers, and X-ray sensors.
When used in a display, the electrons emitted by a field emission device are directed to a cathodoluminescent material. These display devices are commonly called Field Emitter Displays (FEDs). The electrical theory underlying the operation of a FED is similar to that for a conventional CRT. Electrons supplied by a cathode (i.e. base conductor) are emitted from many microtips in the direction of the display surface. The emitted electrons strike phosphors on the inside of the display which excites the phosphors and causes them to momentarily luminesce. An image is produced by the collection of luminescing phosphors on the inside of the display screen. This process is a very efficient way of generating a lighted image.
In a CRT, a single electron gun is provided to generate all of the electrons which impinge on the display screen. A complicated aiming device, usually comprising high power consuming electromagnets, is required in a CRT to direct the electron stream towards the desired screen pixels. The combination of the electron gun and aiming device behind the screen necessarily make a CRT display prohibitively bulky.
FEDs, on the other hand, may be relativelv thin. Each pixel of an FED has its own electron source, typically an array or grouping of emitting microtips. The FEDs are thin because the microtips, which are the equivalent of an electron gun in a CRT, are extremely small. Further, an FED does not require an aiming device, because the electron guns (i.e. the array of microtips) for each pixel are positioned directly behind the screen. The microtips need only be capable of emitting electrons in a direction generally normal to the FED substrate.
As referenced above, a field emission device used in a display may include a microelectronic emission surface, also referred to as a "tip" or "microtip", to enhance electron emissions. Conical, pyramidal, curved and linear pointed tips are often used. Alternatively, a flat tip of low work function material may be provided. The tip may be disposed in a dielectric well that has approximately the same height as the tip. A base conductor may make electrical contact with the bottom of the tip at the base of the well. An extraction electrode or "gate conductor" may be provided along the upper rim of the well, adjacent, but not touching, the field emission tip, to form an electron emission gap therebetween. Upon application of an appropriate voltage between the base conductor and the gate, quantum mechanical tunneling, or other known phenomena, cause the tip to emit electrons. In microelectronic applications, an array of field emission tips may be formed in wells on the horizontal face of a substrate, such as a silicon semiconductor substrate, glass plate, or ceramic plate. Base conductors, gates and other electrodes may also be provided on or in the substrate as necessary. Support circuitry may be fabricated on or in the substrate.
The FEDs may be constructed using various techniques and materials, which are only now being perfected. There are two predominant processes for making field emission devices; "well first" processes, and "tip first" processes. In well first processes, such as a Spindt process, wells are first formed in a material, and tips are later formed in the wells. In tip first processes, the tips are formed first, and the wells are formed around the tips. There are multitudes of variations of both the well first and the tip first processes. The present invention relates primarily to a well first process.
The production of field emission devices using well first processes may require etching the wells into the device. With reference to FIG. 1, an emission array 10 of an FED may be constructed from a multi-layered structure having a bottom substrate 205 with a base conductor 200 formed thereon, a dielectric layer 210 formed on the base conductor 200, and a gate conductor 220 overlying the dielectric layer 210. The gate conductor material used may include materials such as Nb. The substrate 205 may be a glass substrate with layers of metal and insulator deposited thereon to form the base conductor 200 and dielectric layer 210, respectively. Alternatively, the base conductor 200 and dielectric layer 210 may be formed from a silicon wafer having an upper layer of SiO.sub.2 formed therein to provide the dielectric layer.
Emitter wells may be formed in the emission array 10 by providing the gate conductor 220 with a gate hole using a photoresist masking and reactive ion etching (RIE) process on the gate conductor. The photoresist masking process requires that a layer of photoresist 230 be applied to and substantially cover the Nb gate conductor 220. Following an exposure process, the portion of the photoresist layer that is directly above the area where the gate hole is to be formed may be removed so that a hole 232 is formed in the photoresist mask.
With reference to FIG. 2, following the formation of the hole in the photoresist mask, the gate hole 222 may be etched into the gate conductor 220. The thickness of the gate conductor 220 that is used may be limited by the etch's ability to selectively etch the gate conductor and not etch the photoresist mask 230. A thick gate conductor 220 may be advantageous in some applications because it may increase the chance that the emitter tip that is formed later will be in the plane of the gate conductor. Using the above-referenced process, however, if the gate conductor 220 is too thick, the photoresist mask 230 may be etched away before etching through the gate conductor is completed. If the photoresist mask is etched away, the shape and size of the gate hole 222 may be affected undesirably.
Following the formation of the gate hole 222, the dielectric layer 210 may be selectively etched using a chemical etch or RIE to form an emitter well 212 in the dielectric layer. If the dielectric layer 210 is thicker than a predetermined limit, the photoresist mask 230 may be etched away before etching through the dielectric layer is completed. Etching away of the photoresist mask 230 before completion of the etching through the gate conductor 220 and the etching through the dielectric layer 210 may undesirably affect the size and shape of the gate hole 222 and the emitter well 212 that are produced. Degradation of the size and shape of the gate hole and the emitter well as a result of photoresist erosion may be particularly problematic when attempting to make these structures with substantially vertical sidewalls. Photoresist erosion during etching may also make it difficult or impossible to form gate holes and emitter wells with relatively small diametrical dimensions (e.g. 1 micron or less).
The foregoing method of forming emitter wells is also complicated by the fact that it requires two separate and distinct etching steps. A first etching step is required to etch the gate hole 222 into the gate conductor 220 and a second etching step is required to remove dielectric material under the gate hole 222 to form the emitter well 212.
After the gate hole 222 and emitter well 212 are formed, the photoresist layer 230 may be stripped off the device. The photoresist layer must be stripped before the FED is sealed because organic materials, such as photoresist, may outgas significantly over time within the FED. The occurrence of outgassing after an FED is completed and sealed can be catastrophic to the operation of the FED.
Although it is necessary, stripping the photoresist layer undesirably exposes the gate conductor 220 along its entire upper surface. Exposing the upper surface of the gate conductor 220 may present a problem in particular when Nb, or similar types of gate conductors, are used in an FED. The exposed surface of Nb or similar material may corrode during the heating cycles associated with processing and sealing the FED after the gate holes and emitter wells are formed.
It is evident from the foregoing that there is a need for an etch mask useful for the formation of gate holes and emitter wells that does not erode as quickly as photoresist or other organic material etch masks. There is also a need for an etch mask that may protect a FED gate conductor from exposure to corrosive processing and sealing steps during the manufacture the FED. Further, there is a need for an etch mask that enables the production of FED's with thicker gate conductors and thicker dielectric layers. Still further, there is a need for a method of forming gate holes and emitter wells that will require fewer distinct etching steps.